This disclosure relates to electronic circuitry, and more particularly to circuitry for recovering data information from a serial data signal received by the circuitry.
Communication of data between components of a system by means of so-called high-speed serial data signals is of increasing interest and importance to electronic system designers and users. For example, such a signal may have a data bit rate of about 1 gigabits per second (1 Gbps) or more; and data rates much higher than that (e.g., up to 10 Gbps or more) are now in use or at least contemplated. (A bit is a binary digit, typically having a value of either 1 or 0.)
Illustrative use of high-speed serial data signals is for conveying data from one integrated circuit (“IC”) in a system to another IC in the system. For example, these two ICs may be mounted on a printed circuit board (“PCB”), with one or more signal traces on the PCB being used to make a serial data signal connection between the ICs. (A serial data signal may be either a so-called single-ended signal having only one signal constituent and therefore requiring only one conductor (e.g., one PCB circuit trace) to convey it between ICs; or the serial data signal may be a so-called differential signal having two logically complementary signal constituents (one constituent high when the other constituent is low, and vice versa) and therefore requiring two conductors (e.g., two PCB circuit traces) to convey it between ICs. It will generally not matter herein whether the serial data signal is transmitted in single-ended or differential form, and so this possible variation among different systems will usually be ignored in this disclosure. Also, the singular term “serial data signal” will generally be used as a generic term for both single-ended and differential serial data signals (even though a differential serial data signal actually comprises two complementary signal constituents).)
Another example of a system construction in which a high-speed serial data signal may be used for conveying data between two ICs is a construction in which each IC is on a different PCB, and both PCBs are mounted on a so-called back-plane (“BP”) circuit. The serial data signal may be transmitted via circuit traces on the PCBs that are connected to one another via one or more additional circuit traces on the BP.
The foregoing are only some examples of how high-speed serial data signals may be used, and it will be appreciated that there are many other contexts in which such signals may be used.
A problem that is common to many uses of high-speed serial data signals is that they are generally subject to loss of clarity or fidelity as they propagate through whatever medium is used to transmit them. Such loss of fidelity (which can also be characterized using any of many other terms such as signal degradation, attenuation, loss, noise, inter-symbol-interference (“ISI”), etc.) tends to become more of a problem as the data rate (serial bit rate) of the signal increases. In particular, higher frequencies are needed to transmit higher serial data rates; but high frequency signals tend to be more seriously degraded by the transmission media often used for transmission of high-speed serial data signals. Thus (again) the higher the data rate of a serial data signal, the more transmission degradation it is generally subject to.
Degradation of a high-speed serial data signal (e.g., as described above from an IC transmitting that signal through a transmission medium to another IC receiving the signal) increases the difficulty that the receiving (receiver, “RX”) IC has in correctly interpreting the data information in the received signal. For example, some individual bits in the received signal may not achieve adequate or correct voltage differentiation from the threshold voltage that is used by input circuitry of the RX IC to distinguish a binary 1 (e.g., received serial data signal voltage above the threshold voltage) from a binary 0 (e.g., received serial data signal voltage below the threshold voltage). The RX IC may therefore incorrectly interpret the data value of such a bit (e.g., mistakenly interpreting a transmitted (“TX”) binary 1 as a binary 0, or mistakenly interpreting a TX binary 0 as a binary 1.
To help compensate for the signal degradation that can cause or contribute to such RX data interpretation errors, an RX IC may be equipped with any one or more of so-called equalization circuits for early-stage or preliminary processing of a received high-speed serial data signal (e.g., prior to any attempt to recover data information from that signal in more downstream circuitry). In general, the purpose of such equalization circuitry is to try to compensate for or ameliorate degradation that the high-speed serial data signal has been subjected to on its way to the RX IC and thereby improve the reliability of the RX IC in accurately recovering all data information from the received signal. For example, one type of such equalizer circuitry is so-called decision feedback equalizer (“DFE”) circuitry.
As the serial data bit rate of a high-speed serial data signal increases, the number of “taps” required in a DFE circuit in order for that circuit to remain an effective equalizer for the signal tends to increase. Each tap typically includes a circuit for multiplying a respective earlier (previously received) data bit value (e.g., the kth data bit value prior to the current bit) by a respective tap coefficient Ck and additively combining all of the resulting products with the incoming signal for the current bit. (“Additively combining” is used herein as a generic term that may include addition, subtraction, or any combination thereof.) If only a small number of taps is required, it may not be too difficult to find an optimal set of DFE tap coefficient values by, for example, a trial-and-error approach in which various combinations of different coefficient values are tried until an acceptably low bit error rate (“BER”) is achieved by the RX IC in recovering data information from the received serial data signal. Such an approach becomes less acceptable as the number of taps needed in the DFE circuitry increases (e.g., to provide effective equalization for serial data signals with higher serial data bit rates). Also, some systems of the general type being discussed herein may require so-called adaptive equalization in which the DFE tap coefficients change from time to time (or on an on-going or continuous basis) to keep the DFE circuitry performing effectively despite possible changes in other aspects of system performance, especially system performance changes that change the degradation experienced by the serial data signal on its way to the RX IC. Especially for systems requiring such adaptive equalization, it is desirable to automate the determination (calculation, recalculation) of DFE tap coefficient values, and to be able to perform such automated determinations efficiently (e.g., without excessive processing power and/or processing circuitry being required).